Silicon wafers used to manufacture Integrated circuit chips inevitably include some defects that can result in errors in the integrated circuits when etched onto the wafers. Different types of defects can occur at different locations in the wafer. For example, surface adhesions where pieces of the top layer of the wafer have been pulled away from the body of the wafer typically occur on the front or back face of the wafer. Edge defects occur around the perimeter of the wafer. Slip line cracks typically occur along crystal lattice lines. Detecting of all of these different types of defects has proved to be a challenging task.
Prior silicon wafer defect detection technologies have not adequately addressed the challenges of determining thickness variations in silicon wafers and detecting the different types of defects that occur in the wafers used to manufacture integrated circuit chips. This results in the inefficient fabrication of defective chips. There is, therefore, a need for more effective methods and systems for detecting various types of defects in silicon wafers prior to etching the integrated circuits onto the wafers.